In current memory systems, data stored in volatile memories (e.g., in dynamic random access memory, DRAM) must be refreshed periodically to compensate for inherent leakage of capacitors in each of the memory cells. Refreshing includes, for example, reading data out of each row of memory and subsequently writing the data back to the same respective row. As a result, the original charge level on each capacitor is restored and data are preserved.
However, data stored in rows of memory physically adjacent a repeatedly accessed row may be disturbed and may degrade more quickly than data stored in other rows. That is, due to coupling effects between adjacent rows, cell-to-cell leakage may increase, and accessing a row a relatively high number of times (e.g., hundreds of thousands) during a particular period of time (e.g., less than 32 msec) may degrade data stored in rows physically adjacent or otherwise proximate to the accessed row. This phenomenon is referred to as “row hammering.”
Presently, there are various types of techniques and systems used for row-hammer repair (RHR) in order to refresh memory lines adjacent a hammered row. However, these approaches have struggled when applied to the increasingly demanding operating speeds and applications of contemporaneous memories. For example, in one technique, the number of times every row within a memory array (or banks of memory arrays) is accessed is tracked and recorded. Rows adjacent the accessed rows are then sent a refresh signal. However, maintaining counts in this manner is cumbersome and requires a relatively large footprint for the associated circuitry. In other techniques, sampling of activated rows is employed. However, the sampled activation row is always tied to the refresh interval. As a result, the probability of a missed activations is greater than desired and, consequently, a proper RHR cannot be accomplished.